The present disclosure relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device including a silicide layer.
Improvement in the integration degree of a semiconductor device has reduced an area occupied by the semiconductor device while increasing resistances of gate patterns and word lines, which leads to deteriorated characteristics of the semiconductor device. Particularly, a non-volatile memory device performing a program/erase operation on a page basis has a program of decreased program/erase operation rate due to an increase in the resistance of word lines because the distance between each memory cell and a decoder is different. Therefore, conventional technologies seek to decrease the resistance by forming gate patterns and word lines by using a metal silicide layer having a low resistance value.
Hereafter, a conventional method for fabricating a gate pattern and drawbacks of the conventional method will be described with reference to the accompanying drawings.
FIGS. 1A to 1D are cross-sectional views describing a conventional method for forming gate patterns. Referring to FIG. 1A, gate patterns 11 are formed over a substrate 10. The gate patterns 11 may be gate patterns of a Dynamic Random Access Memory (DRAM) device or gate patterns of a non-volatile memory device. In the case of a gate pattern of a DRAM device, the gate pattern includes a gate insulation layer and a gate electrode. In the case of a gate pattern of a non-volatile memory device, the gate pattern includes a tunnel insulation layer, a charge trapping layer, a charge blocking layer, and a gate electrode. Herein, only a gate electrode is illustrated for the sake of convenience in description.
Subsequently, an interlayer dielectric layer 12 is formed over the substrate with the gate patterns 11 formed therein and a planarization process is performed until the uppermost surface of each gate pattern 11 is exposed.
Referring to FIG. 1B, the interlayer dielectric layer 12 is etched back to expose the upper portion of each gate pattern 11. Herein, the etched interlayer dielectric layer is denoted with a reference numeral 12A.
Referring to FIG. 1C, a metal layer 13 is formed over the substrate with the gate patterns 11 having an exposed upper portion.
Referring to FIG. 1D, the upper portion of each gate pattern 11 is silicified by having the metal layer 13 react with the upper portions of the gate patterns 11 through a thermal treatment. Herein, the gate patterns having a silicified upper portion are denoted with a reference numeral 11A. Subsequently, unreacted metal layer 13 is removed during the thermal treatment.
According to the conventional technology described above, the upper portion of each gate pattern 11, which is a gate electrode, may be metal-silicified. However, the width W of the gate electrode decreases due to a procedural limitation, while the gate patterns 11 are formed and silicified. The decreased width W of the gate electrode increases not only the resistance of the gate electrode, but also the surface resistance of word lines as well, thereby deteriorating the read/write rate of a DRAM device or the program/erase rate of a non-volatile memory device.
Hereafter, problems of conventional technology for forming gate patterns will be described specifically with reference to FIGS. 2A to 2C.
FIG. 2A illustrates a cross section of an intermediate resultant substrate with gate patterns 21 having the upper portion exposed by performing an etch-back of an interlayer dielectric layer 22. FIG. 2A corresponds to FIG. 1B described before.
As illustrated, during the etch-back process of the interlayer dielectric layer 22, the margins of a gate pattern 21 (see region labeled B in FIG. 2A) is damaged. In other words, silicon (Si) of the gate electrode is lost. In this case, the gate electrode lacks an adequate silicon source and a silicidation reaction is not performed sufficiently during a subsequent silicidation process.
In particular, the width of the upper portion of the gate electrode is decreased due to the damage of the gate pattern 21. Accordingly, the upper portion of the gate pattern 21 comes to have a conical shape (see region labeled A in FIG. 2A), thus increasing the resistance of the gate electrode.
Also, the surface of the gate pattern 21 may be damaged by a plasma gas during the etch-back process of the interlayer dielectric layer 22, and an impurity layer (see reference indicator C in FIG. 2A) may be formed on the surface due to impurities.
FIG. 2B illustrates a cross section of an intermediate resultant substrate with a metal layer 23. The drawing corresponds to FIG. 1C. As illustrated in the drawing, when the metal layer 23 is formed over the gate pattern 21 with its upper portion whose width is decreased, the metal layer 23 is not uniformly deposited over the upper portion of the gate pattern 21. Rather, it is deposited disproportionally on one side, which is a problem.
FIG. 2C illustrates a cross section of the upper portion 24 of a gate pattern 21A. The drawing corresponds to FIG. 1D. As described above, since the width of the upper portion 24 of the gate pattern 21A is decreased by the damage during the etch-back process, the gate electrode lacks an adequate silicon source to be used during a silicidation process. Accordingly, the width W1 of the upper portion 24 of the gate pattern 21A is decreased even more, thereby increasing the resistance of the gate electrode. As a result, the surface resistance of word lines increases, and the read/write operation rate of a DRAM device or a program/erase operation rate of a non-volatile memory device is decreased.
When an impurity layer (see reference indicator C) is formed over the surface of the upper portion of the gate pattern 21 during the etch-back process of the interlayer dielectric layer 22, impurities permeate during the silicidation process and inhibit the silicidation of the gate pattern 21.
Also, when the uppermost portion of the gate pattern 21 has a conical shape, the metal layer 23 is disproportionally deposited on one side of the upper portion of the gate pattern 21. Thus, there is a problem in that the gate pattern 21 inclines (see reference indicator D) or is broken (see reference indicator E).
In addition, to form a metal silicide layer having a small resistance value, the silicon of the gate pattern may be amorphous or of a small grain size. However, a thermal treatment crystallizes the silicon or increases the size of the grains. Therefore, even though a metal silicide layer is formed, the quality of the metal silicide layer is poor, and thus, the surface resistance increases.
The aforementioned problems become worse as the integration degree of a semiconductor device increases. At a high integration degree, the width of the gate pattern 21 is decreased, and thus, relatively more silicon is lost during the etch-back process. Thus, the silicidation process is not performed smoothly due to lack of the silicon source. Moreover, since the width of the upper portions 24 of the silicified gate patterns 21A are decreased, the chances that the upper portions 24 of the silicified gate patterns 21A become inclined or broken are high. In sum, as the integration degree increases, the imbalance in line width of the silicified gate patterns 21A becomes severe due to procedural limitations, and this leads to a problem of increased resistance values.
FIG. 2D shows a picture of the gate patterns inclining according to conventional technology. As illustrated in the drawing, the lack of silicon source and the unbalanced deposition of the metal layer 23 decreases the width of the gate patterns and makes the gate pattern incline.